By P. Antognetti, F. Anceau and J. Vuillemin (Editors)
ISBN-10: 9024732026
ISBN-13: 9789024732029
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Additional resources for Microarchitecture of VLSI Computers (NATO Advanced Science Institutes Series E: Applied Sciences - No. 96)
Example text
When the Flowcharts say: al Notes: 1. 'al': start executing a new S/370 instruction. Figure 46. Macrocycles. 6 Macrocycles. Certain System/370 instructions and PSW swaps (during interruption processing) require an uninterruptible sequence of bus cycles. They must read data, modify them, and then store the modified data without allowing any other device attached to the bus to access the same data. Micro/370 supports such read-modify-write operations with its Macrocycle. Figure 46 explains how the Processor controls Macrocycles.
2. Output data are rightjustified with leading Os. Figure 19. AG constants. nitions call the instruction fields which designate a register 'RI', 'R2', 'R3', 'X2', 'Bi', and 'B2'. The Micro/370 Flowcharts call those same fields 'RI', 'R2', 'R2', 'X2', 'RB', and 'RB', respectively. The RB register field is part of the second or third halfword of the instruction; it is the base register for an operand When the Flowcharts sa-: Then Register Control says: -- ra(O:3) a-rl ire(8:11) a-r2 ire(12:15) a-r1(i) a-r2(1) a-re1 ire(8:10) - ra(0:2); ire(12:14) .
Likewise, the CSA Multiplexer recognizes when the E-Unit is using the contents of DI to calculate an operand address from a base register and a displacement. When DIX signals that the halfword in the lower half of DI is invalid, the Multiplexer chooses the CSA from the DIX PLA, and Micro/370 generates an appropriate interruption. In both cases, Micro/370 does not signal the Bus Access error in prefetching instructions until it actually requires the instruction. This is a requirement of System/370 architecture.
Microarchitecture of VLSI Computers (NATO Advanced Science Institutes Series E: Applied Sciences - No. 96) by P. Antognetti, F. Anceau and J. Vuillemin (Editors)
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