By Thomas Frederiksen
ISBN-10: 0070219702
ISBN-13: 9780070219700
ISBN-10: 0070219710
ISBN-13: 9780070219717
This can be the 1st approved textual content to track the $64000 steps within the evolution of IC strategies. additionally scans such new frontiers as electronic architectures, silicon circuits, VLSI software program, and extra. a good sourcebook for a person in electronics applied sciences.
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Additional resources for Intuitive CMOS electronics: the revolution in VLSI, processing, packaging, and design
Sample text
This was again offset with the -TC of a VBE to obtain an overall low-voltage reference, with essentially a aTe. 2V. 2 Voc R, Fig. 1-15 Basic Band-Gap Voltage Reference , band-gap energy of silicon. This removed the requirement for a high input voltage, reduced the noise, and improved the long-time stability of these band-gap reference voltages, as compared to the earlier zener-diode derived reference voltages. One of the early OTC voltage reference circuits that made use of this concept is shown in Figure 1-15.
A major step forward came from the early realization that a very significant circuit performance advantage resulted from the natural component matching of both the resistors and the transistors that were simultaneously fabricated and were also in proximity on an integrated circuit. Although the initial tolerance was poor, the components would have good ratio matching. The goal was to design circuits with only ratio dependence. This component matching was good enough to allow a transistor to be voltage-biased by the base-emitter forward voltage drop (the ON voltage) of a diode-connected reference transistor, as shown in Figure 1-14.
This change of bias current flow through Q3 and lor Q4 is used to alter the dc gatesource biasing voltage of these source followers and thereby adjust the offset voltage of the overall op amp. To eliminate any stress-related shifts in the trimmed offset voltage, the trimistor should be accessable for trimming in the packaged IC. In the past, this has required additional package pins to allow accessing the onchip trimming circuitry. In this op amp, the existing pins were also used for in-package trim by making use of the circuit shown in Figure 1-29 Background on Solid-State Electronics + vee T ~-------------------4----~+ OUTPUT A BIPOLAR OP AMP °3 ~~----------~yr----------~/ INPUT JFET SOURCE FOLLOWERS Fig.
Intuitive CMOS electronics: the revolution in VLSI, processing, packaging, and design by Thomas Frederiksen
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