By Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech
Discovering new fabrics for copper/low-k interconnects is necessary to the continued improvement of machine chips. whereas copper/low-k interconnects have served good, making an allowance for the construction of extremely huge Scale Integration (ULSI) units which mix over one thousand million transistors onto a unmarried chip, the elevated resistance and RC-delay on the smaller scale has develop into a major factor affecting chip functionality.
Advanced Interconnects for ULSI Technology is devoted to the fabrics and strategies that can be compatible replacements. It covers a huge diversity of issues, from actual rules to layout, fabrication, characterization, and alertness of latest fabrics for nano-interconnects, and discusses:
- Interconnect services, characterisations, electric houses and wiring necessities
- Low-k fabrics: basics, advances and mechanical houses
- Conductive layers and boundaries
- Integration and reliability together with mechanical reliability, electromigration and electric breakdown
- New methods together with 3D, optical, instant interchip, and carbon-based interconnects
Intended for postgraduate scholars and researchers, in academia and undefined, this publication offers a severe evaluation of the allowing know-how on the center of the longer term improvement of machine chips.
Chapter 1 Low?k fabrics: fresh Advances (pages 1–33): Geraud Dubois and Willi Volksen
Chapter 2 Ultra?Low?k through CVD: Deposition and Curing (pages 35–77): Vincent Jousseaume, Aziz Zenasni, Olivier Gourhant, Laurent Favennec and Mikhail R. Baklanov
Chapter three Plasma Processing of Low?k Dielectrics (pages 79–128): Hualiang Shi, Denis Shamiryan, Jean?Francois de Marneffe, Huai Huang, Paul S. Ho and Mikhail R. Baklanov
Chapter four rainy fresh functions in Porous Low?k Patterning tactics (pages 129–171): Quoc Toan Le, man Vereecke, Herbert Struyf, Els Kesters and Mikhail R. Baklanov
Chapter five Copper Electroplating for On?Chip Metallization (pages 173–191): Valery M. Dubin
Chapter 6 Diffusion boundaries (pages 193–234): Michael Hecker and Rene Hubner
Chapter 7 technique Integration of Interconnects (pages 235–265): Sridhar Balakrishnan, Ruth mind and Larry Zhao
Chapter eight Chemical Mechanical Planarization for Cu–Low?k Integration (pages 267–289): Gautam Banerjee
Chapter nine Scaling and Microstructure results on Electromigration Reliability for Cu Interconnects (pages 291–337): Chao?Kun Hu, Rene Hubner, Lijuan Zhang, Meike Hauschildt and Paul S. Ho
Chapter 10 Mechanical Reliability of Low?k Dielectrics (pages 339–367): Kris Vanstreels, Han Li and Joost J. Vlassak
Chapter eleven electric Breakdown in complicated Interconnect Dielectrics (pages 369–434): Ennis T. Ogawa and Oliver Aubel
Chapter 12 3D Interconnect expertise (pages 435–490): John U. Knickerbocker, Lay Wai Kong, Sven Niese, Alain Diebold and Ehrenfried Zschech
Chapter thirteen Carbon Nanotubes for Interconnects (pages 491–502): Mizuhisa Nihei, Motonobu Sato, Akio Kawabata, Shintaro Sato and Yuji Awano
Chapter 14 Optical Interconnects (pages 503–542): Wim Bogaerts
Chapter 15 instant Interchip Interconnects (pages 543–563): Takamaro Kikkawa
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Extra resources for Advanced Interconnects for ULSI Technology
On the other hand, the stiffness of controlled-collapsed-chip-connection (C4) solders has increased with the switch to lead-free materials and ceramic carriers have been replaced by organic substrates (with a higher coefficient of thermal expansion (CTE) and lower Young’s modulus). Altogether, more thermomechanical stress is applied to the BEOL levels whereas the overall fracture resistance of the structure has been reduced. 1 [54, 55]. 1 that the preferred evolution of BEOL and packaging characteristics is the mirror image to what is currently developed in the semiconductor industry.
After the die is assembled in a flip-chip package, a significant increase of this ERR was obtained for the interconnect structure interfaces parallel to the die surface. In a two-metal layer interconnect structure, the ERR was shown to increase rapidly when the modulus of the ILD is lower than 10 GPa . In a more complex structure, the interface exposed to the highest ERR varies as a function of the materials (TEOS, low-k and ULK) used at each interconnect level . For a full interconnect structure based on the 65 nm technology node, the ERR increased with increasing crack length.
In that regard, Liu et al. have developed an ‘evaporation-assisted two-stage synthesis that apparently limits the formation of 40–80 nm zeolite nanoparticles in solution leading to low-k films with improved properties’ . g. 14 nm) could be obtained in a 63 % yield using this strategy. Unfortunately, spincoating of the above formulation leads to low-k films containing pores as wide as 50 nm, as evidenced by a comparative study conducted by a different group . Remarkably, it was recently discovered that crystallization can also occur during the annealing of the spin-on films in a new process called ‘on-wafer crystallization’ .
Advanced Interconnects for ULSI Technology by Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech