By João Goes, João C. Vital, José Franca (auth.)
ISBN-10: 0306481936
ISBN-13: 9780306481932
ISBN-10: 0792372913
ISBN-13: 9780792372912
Systematic layout for Optimisation of Pipelined ADCs proposes and develops new concepts, methodologies and instruments for designing low-power and low-area CMOS pipelined A/D converters. the duty is tackled via following a scientifically-consistent technique. to start with, the cutting-edge in pipeline A/D converters is analysed with a double objective: a) to spot the simplest applicable between diverse techniques suggested in literature and taking into consideration the pursuits pursued; b) to spot the drawbacks of those concepts as a uncomplicated first step to enhance them. Then, the ebook proposes a top-down layout technique for enforcing high-performance low-power and low-area CMOS pipelined A/D converters via:
The proposed procedure is absolutely based on the easiest perform in regards to the layout of mixed-signal built-in circuits. at the one hand, drawbacks of presently current options are overcame via cutting edge concepts and, nonetheless, the specialist wisdom is packaged and made on hand for re-usability by way of the neighborhood of circuit designers. ultimately, feasibility of the techniques and the linked encapsulated wisdom is granted via experimental validation of operating silicon.
Systematic layout for Optimisation of Pipelined ADCs serves as an outstanding reference for analogue layout engineers specifically designers of low-power CMOS A/D converters. The booklet can also be used as a textual content for complicated examining at the subject.
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This additional redundancy allows digital correction of the MSBs depending on the value of the extra bit. Therefore, if the extra bit is “1”, a logical “1” must be added or subtracted to 20 2. General Design Considerations in Pipelined A/D Converters the previous quantization (MSBs), respectively, for the upper or lower range of correction. If the extra bit is “0” no operation is performed. 2 RESIDUE AMPLIFICATION GAIN-ERROR IN THE MDACS For a given pipelined stage, a gain error in the residue amplification can cause the residue range to be smaller or larger than the conversion range of the following stage.
820-827, December 1984. 4] Bang-Sup Song, Seung-Hoon Lee, Michael F. Tompsett, "A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter", IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, pp. 1328-1338, December 1990. -H. Lee, Bang-Sup Song, "Simplified Digital Calibration for Multi-Stage Analog-toDigital Converters", Proc. IEEE International Symposium on Circuits and Systems, pp. 1216-1219, Chicago, USA, 1993. 6] Sehat Sutarja and Paul R. Gray, "A Pipelined 13-bit, 250-ks/s, 5-V Analog-to-Digital Converter", IEEE Journal of Solid-State Circuits, Vol.
Additional information concerning the complete electrical schematics as well as the detailed design of all of these building blocks will be given later on, in Chapter 5, where the design of a 14-bit 5 MS/s pipelined ADC is described. 9 shows a microphotograph of the complete die, where the blocks REFDAC, 4-bit MDAC, 12-bit CALDAC and HAC occupy and dissipate less than 60 mW. 3. 11 shows the corresponding INL errors for the 16 possible input codes. As expected, the measured INL errors are roughly compatible with the 14 bit level.
Systematic Design for Optimisation of Popelined ADCs by João Goes, João C. Vital, José Franca (auth.)
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