By Thorsten Baumheinrich, Bernd Prégardier, Ulrich Langmann (auth.), Rudy J. van de Plassche, Hohan H. Huijsing, Willy Sansen (eds.)
`The authors are to be complimented for accumulating, right into a unmarried reference, loads of fascinating details concerning the above pointed out themes, quite worthwhile for data-acquisition approach designers, RF engineers, and others.'
Microelectronics magazine 29 (1998) 1039-1046
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Additional info for Analog Circuit Design: RF Analog-to-Digital Converters; Sensor and Actuator Interfaces; Low-Noise Oscillators, PLLs and Synthesizers
1997 Kluwer Academic Publishers. 26 This paper will focus on CMOS AID converters for high frequency low power applications. In section 2 a folding AID converter architecture will be presented, that is able to fulfill the speed and performance requirements. In section 3 the main CMOS technology trends will be given. The main parameters of the technology make it possible to extrapolate the supply voltage requirements, bandwidth and power relations of the AID converter in advanced CMOS technologies (section 4).
In Figure 16 the harmonic distortion as a function of input frequency is shown at a clock frequency of 40 MHz. Clearly, harmonic distortion is the limiting factor for the maximum analog input frequency of 12 MHz. 2 MHz, analyzed via a 10-bit D/A converter. In Table 1 the measured AID converter parameters have been summarized. Low voltage, low power operation had the highest priority in this design. This is indicated by the Figure of Merit (FOM) of the AID converter. The FOM is defined as follows: FOM= p·rn (28) FCLK with P the power dissipation, n the number of bits of the AID converter and F eLK the maximum clock frequency.
The input capacitance Cn is proportional to the gate source capacitance of a cascaded amplifier. This capacitance depends on the size of the differential pair transistors. The offset of the cascaded amplifier is allowed to be larger than the offset of its preceding stage: it is assumed that the offset of the cascaded amplifier can be divided by the gain A of the preceding gain stage. This leads to the following expression of Cn: 2 Cin = 3A WLCox . 1 CoxVGT 2 27rL(3CoxL+ AC) (18) Notice that in this equation the bandwidth is independent of power dissipation: it should be considered as an absolute maximum bandwidth, given the technology parameters L, Cox, Cj and the chosen linearity parameter VGTand the DC gain A.
Analog Circuit Design: RF Analog-to-Digital Converters; Sensor and Actuator Interfaces; Low-Noise Oscillators, PLLs and Synthesizers by Thorsten Baumheinrich, Bernd Prégardier, Ulrich Langmann (auth.), Rudy J. van de Plassche, Hohan H. Huijsing, Willy Sansen (eds.)