By Naresh Maheshwari
ISBN-10: 1461375797
ISBN-13: 9781461375791
ISBN-10: 1461556376
ISBN-13: 9781461556374
Recent years have noticeable swift strides within the point of class of VLSI circuits. at the functionality entrance, there's a important desire for strategies to layout quickly, low-power chips with minimal quarter for more and more advanced platforms, whereas at the monetary part there's the drastically elevated strain of time-to-market. those pressures have made using CAD instruments essential in designing advanced platforms.
Timing research and Optimization of Sequential Circuits describes CAD algorithms for studying and optimizing the timing habit of sequential circuits with particular connection with functionality parameters akin to strength and sector. A unified method of functionality research and optimization of sequential circuits is gifted. The cutting-edge in timing research and optimization suggestions is defined for circuits utilizing edge-triggered or level-sensitive reminiscence components. particular emphasis is put on equipment which are precise sequential timing optimizations strategies: retiming and clock skew optimization.
Timing research and Optimization of Sequential Circuits covers the next issues:
- Algorithms for sequential timing research
- Fast algorithms for clock skew optimization and their purposes
- Efficient innovations for retiming huge sequential circuits
- Coupling sequential and combinational optimizations.
Timing research and Optimization of Sequential Circuits is written for graduate scholars, researchers and pros within the region of CAD for VLSI and VLSI circuit design.
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Sample text
4. H-tree layout for clocking. In contrast with the bottom-up approach used in both of these methods, the method of means and medians [JSK90] works in a top-down manner, recursively bipartitioning the routing area into subregions. The centers of these regions are connected appropriately, with the aim of generating at a balanced tree in which the distance from the clock source to the sinks is minimized. 2 Exact Zero-skew Clock Routing Each of the methods described so far simplifies the problem of equalizing the clock delays into the geometric problem of equalizing the path lengths on a Manhatan grid.
We will now describe this method in detail, and explain how it may be extended to build clock trees with specified, and possibly nonzero, skews at the sink nodes. The Elmore delay model [RPH83] is used to calculate the signal propagation delay from a clock source to each clock sink. A modified hierarchical method is proposed for computing these delays in a bottom-up fashion. This algorithm takes advantage of the structure of the Elmore delay calculations to construct a recursive bottom-up procedure for interconnecting two zero-skew subtrees to form a new tree with zero skew.
Rl ell -=c i Iltl~ l. ±.. 5. subtree 2 ............. .............. ... . ±.. .............. : C2 : ~ Zero-skew merge of two subtrees [Tsa93] @1993 IEEE. 2) results in a value x that satisfies ~ x ~ 1, then the tapping point lies along the segment interconnecting the two subtrees and is legal. In case x lies outside this range, it implies that the loads on the two subtrees are too disparate. If so, the tapping point is set to lie at the root of the subtree with the larger loading, and the wire connected to the other segment is elongated in order to ensure that its additional delay balances the delay of the first subtree.
Timing Analysis and Optimization of Sequential Circuits by Naresh Maheshwari
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