By Dr.-Ing. Keh-La Lin, Armin Kemna, Prof. Bedrich J. Hosticka (auth.)
ISBN-10: 0306487268
ISBN-13: 9780306487262
ISBN-10: 1402073801
ISBN-13: 9781402073809
One of the most developments of microelectronics is towards layout for built-in platforms, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). because of this improvement, layout strategies for mixed-signal circuits develop into extra very important than prior to. between different units, analog-to-digital and digital-to-analog converters are the 2 bridges among the analog and the electronic worlds. in addition to, low-power layout method is likely one of the major matters for embedded platforms, specially for handheld applications.
Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems goals at layout thoughts for low-power, high-speed analog-to-digital converter processed through the normal CMOS expertise. also this booklet covers actual integration problems with A/D converter built-in in SoC, i.e., substrate crosstalk and reference voltage community layout.
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Extra info for Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems
Sample text
It is based on a "weighting" concept. The block diagram of a simplified successive approximation register A/D converter is illustrated in Fig. 17. At the beginning of the conversion process, the MSB of the DAC input signal is set to "1" and the rest bits of the DAC input signal are set to "0", in order to place the DAC output signal to the middle voltage of the conversion range. At the same time, the analog input signal is sampled using a SHA front-end component. During the first clock cycle, the SHA output signal and the DAC output signal are compared by a comparator.
At the beginning of the conversion process, the MSB of the DAC input signal is set to "1" and the rest bits of the DAC input signal are set to "0", in order to place the DAC output signal to the middle voltage of the conversion range. At the same time, the analog input signal is sampled using a SHA front-end component. During the first clock cycle, the SHA output signal and the DAC output signal are compared by a comparator. e. DAC or SHA output, is higher and this MSB is stored in the register.
Of course, this causes an increase of the die area and power dissipation. 40 Chapter 2 The folding and interpolating A/D converter contains two separate converters, namely, the coarse and the fine converter. The input signal is fed into both converters in parallel. For a converter exhibiting total m+n-bit resolution, the m-bit coarse converter contributes the bits of the higher m-bit resolution, beginning from the MSB of the whole A/D converter. The n-bit fine converter generates the remaining lower n-bits, which ends with the LSB of the whole A/D converter.
Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems by Dr.-Ing. Keh-La Lin, Armin Kemna, Prof. Bedrich J. Hosticka (auth.)
by Charles
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