By Andrea Bondavalli, Felicita Di Giandomenico (eds.)
This e-book constitutes the refereed lawsuits of the 33nd overseas convention on machine defense, Reliability, and protection, SAFECOMP 2014, held in Florence, Italy, in September 2014. The 20 revised complete papers provided including three functional event stories have been conscientiously reviewed and chosen from eighty five submissions. The papers are equipped in topical sections on fault injection thoughts, verification and validation options, automobile structures, assurance versions and mitigation innovations, insurance circumstances and arguments, method research, safety and belief, notations/languages for security comparable points, defense and security.
Read Online or Download Computer Safety, Reliability, and Security: 33rd International Conference, SAFECOMP 2014, Florence, Italy, September 10-12, 2014. Proceedings PDF
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Extra info for Computer Safety, Reliability, and Security: 33rd International Conference, SAFECOMP 2014, Florence, Italy, September 10-12, 2014. Proceedings
Vehicle System Dynamics 49(5), 723–739 (2010) 17. 1, 2003/06/12 (2003) 16 I. Ayestaran et al. 18. : Fault Injection Techniques and their Accelerated Simulation in SystemC. In: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007, pp. 587–595 (2007) 19. : An Optimized Simulation-Based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault Coverage. In: 2009 10th International Workshop on Microprocessor Test and Veriﬁcation (MTV), pp. 55–60 (2009) 20.
Job mode job emerg Comm. ch. Core 1 job odo C. c. Processor Core 2 job serv C. c. Core2 Node C. ch. Processor Core1 Cluster Core C. c. job dmi Processor Node Processor job voter Core C. c. Node DMI Core C. c. Node voter Core C. c. Node voter Processor Node Processor C. c. Node EVC C. c. Node EVC Comm. channel Node EVC Fig. 3. SUT: Railway signaling system modeled at PSM level nodes containing a single-core processor, whereas the each EVC node contains a dual-core processor. The ﬁrst core of the processor is the host for the odometry, mode-control and emergency-brake-system jobs, whereas the service-brake system job is hosted on the second core.
Initially we run a ﬁxed number of 100,000 FI experiments4 per benchmark to gain training data. Then the genetic algorithm is initialized with a population of randomized projection vectors. , projection bit vector’s) ﬁtness is evaluated by 1. performing the aforementioned grouping of def/use classes from the training set into similarity classes, 2. picking the largest5 def/use class in each similarity class as the pilot and pretending it properly represents the remaining class members, and 3. measuring the two ﬁtness criteria accuracy and the emerging number of fault-similarity classes within the training set.
Computer Safety, Reliability, and Security: 33rd International Conference, SAFECOMP 2014, Florence, Italy, September 10-12, 2014. Proceedings by Andrea Bondavalli, Felicita Di Giandomenico (eds.)