By David Basin, Felix Klaedtke, Samuel Müller (auth.), Tayssir Touili, Byron Cook, Paul Jackson (eds.)
ISBN-10: 3642142958
ISBN-13: 9783642142956
This publication constitutes the refereed court cases of the twenty second overseas convention on computing device Aided Verification, CAV 2010, held in Edinburgh, united kingdom, in July 2010 as a part of the Federated common sense convention, FLoC 2010. The 34 revised complete papers offered including 17 instrument papers, four invited talks and three invited tutorials have been rigorously reviewed and chosen from one zero one normal paper and forty four device paper submissions. The papers are devoted to the development of the idea and perform of computer-assisted formal research equipment for and software program structures. they're prepared in topical sections on software program version checking; version checking and automata; instruments; counter and hybrid structures verification; reminiscence consistency; verification of and occasional point code; synthesis; concurrent software verification; compositional reasoning; and determination techniques.
Read Online or Download Computer Aided Verification: 22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010. Proceedings PDF
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Extra resources for Computer Aided Verification: 22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010. Proceedings
Example text
5. The results are shown in Table 1. Columns “AIG” and “FF” show the numbers of AIG nodes and registers. The runtimes for different amounts of input patterns are shown in the last columns. 3M AIG nodes. In all four cases, the 2,560 patterns were sufficient for node switching activity rates to converge to a steady state. Table 1. 2 In the second experiment, we compare the runtime of SimSwitch vs. 0 on 14 industry designs and 12 large academic benchmarks. 5 for both tools. The number of input patterns is assumed to be 5,000 for both runs.
Table 1. 2 In the second experiment, we compare the runtime of SimSwitch vs. 0 on 14 industry designs and 12 large academic benchmarks. 5 for both tools. The number of input patterns is assumed to be 5,000 for both runs. All circuits are decomposed into AIG netlists before performing the switching estimation. The table of results can be found in [19]. 0. 0. 0 times out on four industrial designs. 6 Optimization and Verification Flows This section describes integrated sequences of transformations applied in ABC.
The goal of optimization by local transformations of an AIG is to reduce both area and delay. 28 R. Brayton and A. Mishchenko Structural hashing of AIGs ensures that all constants are propagated and, for each pair of nodes, there is at most one AND node having them as fanins (up to a permutation). Structural hashing is performed by hash-table lookups when AND nodes are created and added to an AIG manager. Structural hashing was originally introduced for netlists of arbitrary gates in early IBM CAD tools [15] and was extensively used in formal verification [22].
Computer Aided Verification: 22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010. Proceedings by David Basin, Felix Klaedtke, Samuel Müller (auth.), Tayssir Touili, Byron Cook, Paul Jackson (eds.)
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