By Neil H. E. Weste, David Money Harris
ISBN-10: 0321547748
ISBN-13: 9780321547743
For either introductory and complex classes in VLSI layout, this authoritative, accomplished textbook is very available to newbies, but deals remarkable breadth and intensity for more matured readers. The Fourth version of CMOS VLSI layout: A Circuits and structures point of view provides wide and in-depth assurance of the full box of recent CMOS VLSI layout. The authors draw upon wide and school room adventure to introduce today’s so much complicated and potent chip layout practices. They current widely up-to-date assurance of each key component to VLSI layout, and remove darkness from the newest layout demanding situations with sixty five nm approach examples. This booklet comprises unsurpassed circuit-level assurance, in addition to a wealthy set of difficulties and labored examples that supply deep sensible perception to readers in any respect degrees.
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Extra info for CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition)
Sample text
12(b). Note that by DeMorgan’s Law, the inversion bubble may be placed on either side of the gate. In the figures in this book, two lines intersecting at a T-junction are connected. Two lines crossing are connected if and only if a dot is shown. 2 NAND gate truth table A B Pull-Down Network Pull-Up Network Y 0 0 1 1 0 1 0 1 OFF OFF OFF ON ON ON ON OFF 1 1 1 0 k-input NAND gates are constructed using k series nMOS transistors and k parallel pMOS transistors. 13. When any of the inputs are 0, the output is pulled high through the parallel pMOS transistors.
8 shows a way to improve this multiplexer design. 2 B Sketch a static CMOS gate computing Y = (A + B + C) · D. 19 shows such an OR-AND-INVERT-3-1 (OAI31) gate. The nMOS pull-down network pulls the output low if D is 1 and either A or B or C are 1, so D is in series with the parallel combination of A, B, and C. The pMOS pull-up network is the conduction complement, so D must be in parallel with the series combination of A, B, and C. 6 Pass Transistors and Transmission Gates The strength of a signal is measured by how closely it approximates an ideal voltage source.
37(e) are typically formed with ion implantation, they were historically diffused and thus still are often called n-diffusion. Notice that the polysilicon gate over the nMOS transistor blocks the diffusion so the source and drain are separated by a channel under the gate. This is called a self-aligned process because the source and drain of the transistor are automatically formed adjacent to the gate without the need to precisely align the masks. 37(f )). 38(a). Oxide is used for masking in the same way, and thus is not shown.
CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition) by Neil H. E. Weste, David Money Harris
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