Built-in-Self-Test and Digital Self-Calibration for RF SoCs by Sleiman Bou-Sleiman, Mohammed Ismail PDF

By Sleiman Bou-Sleiman, Mohammed Ismail

ISBN-10: 1441995471

ISBN-13: 9781441995476

ISBN-10: 144199548X

ISBN-13: 9781441995483

This e-book will introduce layout methodologies, referred to as Built-in-Self-Test (BiST) and Built-in-Self-Calibration (BiSC), which counterpoint the robustness of radio frequency (RF) and millimeter wave (mmWave) built-in circuits (ICs). those circuits are utilized in present and rising verbal exchange, computing, multimedia and biomedical items and microchips. The layout methodologies offered will lead to bettering the yield (percentage of operating chips in a excessive quantity run) of RF and mmWave ICs with the intention to permit winning production of such microchips in excessive quantity.

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Extra resources for Built-in-Self-Test and Digital Self-Calibration for RF SoCs

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In zero-IF systems, an image still exists: the signal itself. Apart from amplitude modulated (AM) signals, the upper and lower side lobes of a certain band of interest are not necessarily symmetrical, as is the case for frequency and phase modulation. e. the distinct upper and lower side lobes now overlap and corrupt each other (Fig. 6). The same phenomenon happens at the second and final conversion of a heterodyne system. To overcome this limitation, a phase and frequency decoupling mechanism is needed – hence enters quadrature mixing.

RF detectors, much like the test attenuator and switches, are additional circuits and as such their presence needs to be as non-invasive to the system as possible. This places certain requirements on their design. Multiple detectors can be placed along the transmitter and receiver chains, with their outputs forming a low frequency (mostly dc) bus that can be easily digitized for analysis. Test result analysis: The powerful digital backend can also be used to perform test results analysis. Test results can be derived from two sources: the primary digital lane and the auxiliary dc lane.

Alternate tests do not attempt to sense or measure a certain circuit parameter directly but opt to get a reading that can be explained by a set of circuit parameters. Therefore, it presents an attractive alternative for decreasing test time with the possibility of extracting multiple circuit parameters in a single test, and predicting the specifications accordingly. In essence, alternate testing is a correlation testing methodology in which several spaces are mapped to each other: parameter, signature, and specification spaces (Fig.

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Built-in-Self-Test and Digital Self-Calibration for RF SoCs by Sleiman Bou-Sleiman, Mohammed Ismail

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