By David Johns Ken Martin
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Systematic layout for Optimisation of Pipelined ADCs proposes and develops new suggestions, methodologies and instruments for designing low-power and low-area CMOS pipelined A/D converters. the duty is tackled by means of following a scientifically-consistent method. to begin with, the state-of-the-art in pipeline A/D converters is analysed with a double objective: a) to spot the easiest ideal between diverse concepts suggested in literature and taking into consideration the pursuits pursued; b) to spot the drawbacks of those options as a simple first step to enhance them.
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Additional info for Analog Integrated Circuit Design
Compared to use of the hybrid-it model, and thus it is useful for hand analysis. 56 Chapter 1 • Integrated-Circuit Devices and Modelling rb V b o-~'\Iv--' Fig. 34 v, A low-frequency, small-signal T model for an active BJT. 5 DEVICE MODEL SUMMARY As a useful aid, all of the equations for the large-signal and small-signal modelling of diodes, MOS transistors, and bipolar transistors, along with values for the various constants, are listed in the next few pages. 5 Device Model Summary 57 Forward-Biased Diode o, D Is = Aoqn ,( i -- + -LnN A LpN o p) I 10 = se VD/V T VT kT = - q - 26 mY at 300 OK Small-Signal Model of Forward-Biased Diode VT C T = Cd+C j rd = 10 10 Cd = ' T - Cj = - 2C ,o VT L'n Dn 'T = - MOS Transistor Equations The following equations are for n-channel devices-for p-channel devices, put negative signs in front of all voltages.
9 V). It should be noted that the cross-sectional area of the collector-base junction, Ac, is typically much larger than the effective area of the base-emitter junction, AE , which is shown in Fig. 25. This size differential results in Ac C jCO being larger than AE Cjeo, the base-emitter junction capacitance at 0 V bias, despite the lower doping levels. Finally, another large capacitor is C es' the capacitance of the collector-tosubstrate junction. Since this area is quite large, CCS' which is the depletion capacitance that results from this area, will be much larger than either C eb or the depletion capacitance component of C be, that is, Cj .
P-Channel Transistars All of the preceding equations have been presented for n-channel enhancement transistors. In the case of p-channel transistors, these equations can also be used if a negative sign is placed in front of every voltage variable. Thus, VGS becomes VSG' VOS becomes Vs o, V'n becomes -V,p, and so on. The condition required for conduction is now V SG > Vip. where Vtp is now a negative quantity for an enhancement p-channel transistor. 11 The requirement on the source-drain voltage for a p-channel transistor to be in the active region is Vso> VSG + V,p' The equations for ro, in both regions, remain unchanged, because all voltage variables are squared, resulting in positive hole current flow from the source to the drain in p-channel transistors.
Analog Integrated Circuit Design by David Johns Ken Martin